Pong on Assembly

Playable Pong in two forms: a hardware implementation on FPGA (VGA + PS/2) and a full assembly version (pong.s) for a custom 32-bit ISA. The hardware design runs the full game in the VGA controller; the processor is a stub. The assembly version implements the same game logic with MMIO for keyboard and display. Demonstrates RTL design (FSM, sync, PS/2 and VGA interfaces) and assembly-level systems programming for the same application.

Hardware implementation vga_controller.v holds game state in registers: ball position and direction, paddle Y positions, and scores. Tunable parameters include BALL_SIZE=10, PADDLE_H=40, BALL_SPEED=3, PADDLE_SPEED=4. On each vertical sync (cVS) edge, the controller updates paddles from keyboard inputs (W/S left, O/L right, clamped to the play area), advances the ball, handles wall bounce and paddle collision, and applies scoring (ball past paddle resets position; first to 5 wins and freezes the game). Pixel output is derived from the sync generator and game registers. PS2_Interface.v receives scan codes and maps W/S/O/L to key-down state; skeleton.v wires the PLL, stub processor, PS/2, LCD, and VGA controller so that keyboard inputs drive the game directly—the processor is not used for gameplay in this design.

Assembly version (pong.s) The assembly program uses MMIO: $20=2000 (keyboard), $21=3000 (VGA base). Registers hold ball position ($1,$2), velocity ($3,$4), and paddle Y ($5,$6). The main game loop reads the keyboard, moves paddles (with clamping), updates ball position, handles bounces and paddle hits, checks for goals and resets the ball, then writes ball and paddle data to 3000–3003 and branches back. This version is the software counterpart to the hardware Pong and runs on the custom processor from the Custom-Single-Cycle-32-Bit-Processor repo.