Custom Single-Cycle 32-Bit Processor

A single-cycle 32-bit processor in Verilog with a custom MIPS-like ISA (R-type, I-type, J-type). It has a 12-bit PC, instruction memory (imem), data memory (dmem), and regfile; instructions are word-addressed and the PC increments by 1 each cycle. Special registers $r30 and $r31 hold overflow status and jal return address. This design is the execution target for pong.s in the Pong-on-Assembly repo. Demonstrates processor design from ISA definition through datapath and control to synthesis-ready Verilog.

IF: The PC is held in flip-flops; an ALU computes PC+1. Instruction memory is addressed by the PC. When a branch or jump is taken, a bubble (zero) is fed instead of the next instruction; otherwise the fetched word is latched for decode.

ID: The instruction is decoded into opcode, rd/rs/rt, shamt, ALU op, sign-extended immediate, and jump target. Control logic identifies instruction types (e.g. r_type, lw, sw, bne, jal) and drives reg_write, mem_read, mem_write, and alu_src. Read ports are steered (e.g. $r30 for bex exception check) for the correct source operands.

EX: The ALU performs add, sub, and, or, sll, sra as needed. It produces result, not-equal and less-than (for branches), and overflow; overflow writes a status code to $r30. Branch and jump targets select the next PC (j/jal/jr/bex take priority over branch over PC+1).

MEM: The ALU result is the memory address. Stores write data_readRegB; loads read into q_dmem for writeback.

WB: Writeback selects ALU result or load data via mem_to_reg. setx writes the immediate to $r30; jal writes the return address (PC) to $r31.